IDDQ Test: Will It Survive the DSM Challenge?

نویسندگان

  • Sagar S. Sabade
  • D. M. H. Walker
چکیده

As transistor geometries are reduced, leakage current increases. Due to increased levels and process variation, IDDQ test faces difficult challenges for deep sub-micron technologies. Several solutions have been proposed in the literature. This paper provides an overview of some of the solutions. Some views on the future of IDDQ testing are also presented.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results

This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, ∆Iddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of ∆Iddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, a...

متن کامل

Evaluation of Statistical Outlier Rejection Methods for IDDQ Testing

The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods – the Chauv...

متن کامل

Identifying defects in deep-submicron CMOS ICs

Given the oft-cited difficulty of testing modern integrated circuits, the fact that CMOS ICs lend themselves to IDDQ testing is a piece of good fortune. But that valuable advantage is threatened by the rush of semiconductor technology to smaller feature sizes and faster, denser circuits, in line with the Semiconductor Industry Association's (SIA) Roadmap--its forecast for the CMOS IC industry. ...

متن کامل

IDDQ Test: Sensitivity Analysis of Scaling

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has signi cant impact on the e ectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is ...

متن کامل

Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test

The combination of deep sub-micron technologies together with System on Chip complexity has brought the Device Under Test (DUT) Quiescent Supply Current (IDDQ ) into the Milliamps (mA) range. This IDDQ level, modulated by Electrical Parameters and Critical Dimensions Process spreads , makes almost impossible to detect the small current increase caused by the presence of a defect into the DUT. T...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEEE Design & Test of Computers

دوره 19  شماره 

صفحات  -

تاریخ انتشار 2002